\ContribItem{Figure}{fig:cpu:CPU Performance at its Best}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPUs Old and New}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPU Meets a Pipeline Flush}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPU Meets a Memory Reference}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPU Meets an Atomic Operation}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPU Meets a Memory Barrier}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPU Meets a Cache Miss}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:CPU Waits for I/O Completion}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:Hardware and Software: On Same Side}{Melissa Broussard}
\ContribItem{Figure}{fig:count:Waiting to Count}{Melissa Broussard}
\ContribItem{Figure}{fig:SMPdesign:Dining Philosophers Problem}{Kornilios Kourtis}
\ContribItem{Figure}{fig:cpu:Partial Starvation Is Also Bad}{Melissa Broussard}
\ContribItem{Figure}{fig:SMPdesign:Dining Philosophers Problem, Textbook Solution}{Kornilios Kourtis}
\ContribItem{Figure}{fig:SMPdesign:Dining Philosophers Problem, Partitioned}{Kornilios Kourtis}
\ContribItem{Figure}{fig:SMPdesign:Lock Contention}{Melissa McKenney}
\ContribItem{Figure}{fig:SMPdesign:Data Locking}{Melissa McKenney}
\ContribItem{Figure}{fig:SMPdesign:Data and Skew}{Melissa McKenney}
\ContribItem{Figure}{fig:locking:Locking: Villain or Slob?}{Sarah McKenney}
\ContribItem{Figure}{fig:locking:Locking: Workhorse or Hero?}{Sarah McKenney}
\ContribItem{Figure}{fig:debugging:Validation and the Geneva Convention}{Melissa McKenney}
\ContribItem{Figure}{fig:debugging:Rationalizing Validation}{Melissa McKenney}
\ContribItem{Figure}{fig:cpu:Passed-the-stress-test}{Melissa Broussard}
\ContribItem{Figure}{fig:debugging:Choose Validation Methods Wisely}{Melissa McKenney}
\ContribItem{Figure}{fig:advsync:CPUs Can Do Things Out of Order}{Melissa McKenney}
\ContribItem{Figure}{fig:advsync:Abstract Memory Access Model}{David Howells}
\ContribItem{Figure}{fig:advsync:Write Barrier Ordering Semantics}{David Howells}
\ContribItem{Figure}{fig:advsync:Data Dependency Barrier Omitted}{David Howells}
\ContribItem{Figure}{fig:advsync:Data Dependency Barrier Supplied}{David Howells}
\ContribItem{Figure}{fig:advsync:Read Barrier Needed}{David Howells}
\ContribItem{Figure}{fig:advsync:Read Barrier Supplied}{David Howells}
\ContribItem{Figure}{fig:advsync:Read Barrier Supplied, Double Load}{David Howells}
\ContribItem{Figure}{fig:advsync:Read Barrier Supplied, Take Two}{David Howells}
\ContribItem{Figure}{fig:advsync:Speculative Load}{David Howells}
\ContribItem{Figure}{fig:advsync:Speculative Loads and Barrier}{David Howells}
\ContribItem{Figure}{fig:advsync:Speculative Loads Cancelled by Barrier}{David Howells}
\ContribItem{Figure}{fig:advsync:Memory Architecture}{David Howells}
\ContribItem{Figure}{fig:advsync:Split Caches}{David Howells}
\ContribItem{Figure}{fig:easy:Shaving the Mandelbrot Set}{Melissa McKenney}
\ContribItem{Figure}{fig:future:Uniprocessor Uber Alles}{Melissa McKenney}
\ContribItem{Figure}{fig:future:Multithreaded Mania}{Melissa McKenney}
\ContribItem{Figure}{fig:future:More of the Same}{Melissa McKenney}
\ContribItem{Figure}{fig:future:Crash Dummies Slamming into the Memory Wall}{Melissa McKenney}
\ContribItem{Figure}{fig:future:The STM Vision}{Melissa McKenney}
\ContribItem{Figure}{fig:future:The STM Reality: Conflicts}{Melissa McKenney}
\ContribItem{Figure}{fig:future:The STM Reality: Irrevocable Operations}{Melissa McKenney}
\ContribItem{Figure}{fig:future:The STM Reality: Realtime Response}{Melissa McKenney}
\ContribItem{Figure}{fig:app:questions:What Time Is It?}{Melissa McKenney}
\ContribItem{Figure}{fig:app:whymb:Half Memory Barrier}{Melissa McKenney}
\ContribItem{Figure}{fig:app:rcuimpl:srcu:Sleeping While RCU Reading Considered Harmful}{Melissa McKenney}
\ContribItem{Figure}{fig:SMPdesign:Dining Philosophers Problem, Fully Partitioned}{Kornilios Kourtis}
